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STK20N3LLH5
N-channel 30 V, 0.006 20 A, PolarPAK(R) , STripFETTMV Power MOSFET
Preliminary Data
Features
Type STK20N3LLH5

VDSS 30 V
RDS(on) max < 0.007
RDS(on)*Qg 68 nC*m
Ultra low top and bottom junction to case thermal resistance RDS(on) * Qg industry benchmark Extremely low on-resistance RDS(on) Very low switching gate charge Fully encapsulated die 100% matte tin finish (in compliance with the 2002/95/EC european directive) High avalanche ruggedness PolarPAK(R) is a trademark of VISHAY Figure 1. Internal schematic diagram
PolarPAK(R)
Application
Switching applications
Description
This product utilizes the 5th generation of design rules of ST's proprietary STripFETTM technology. The lowest available RDS(on)*Qg, in this chip scale package, makes this device suitable for the most demanding DC-DC converter applications, where high power density is to be achieved. Table 1. Device summary
Order code STK20N3LLH5 Marking 203L5 Package PolarPAK(R) Packaging Tape and reel
Bottom view
Top view
September 2008
Rev 1
1/13
www.st.com 13
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
STK20N3LLH5
Contents
1 2 3 4 5 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Test circuits .............................................. 6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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STK20N3LLH5
Electrical ratings
1
Electrical ratings
Table 2.
Symbol VDS VGS ID (1) ID IDM (2) PTOT (1)
Absolute maximum ratings
Parameter Drain-source voltage (VGS = 0) Gate-source voltage Drain current (continuous) at TC = 25C Drain current (continuous) at TC = 100C Drain current (pulsed) Total dissipation at TC = 25C Derating factor Value 30 22 20 12.5 80 5.2 0.0416 TBD -55 to 150 Unit V V A A A W W/C J C
EAS (3) Tj Tstg
Single pulse avalanche energy Operating junction temperature Storage temperature
1. When mounted on FR-4 board of 1inch2, 2 oz Cu and 10sec 2. Pulse width limited by package 3. Starting TJ = 25C, ID = 10A, VDD = 25V
Table 3.
Symbol
Thermal data
Parameter Typ. 20 1 2.8 Max. 24 1.2 3.4 Unit C/W C/W C/W
Rthj-amb(1) Thermal resistance junction-amb Rthj-c(2) Rthj-c(3) Thermal resistance junction-case (top drain) Thermal resistance junction-case (source)
1. When mounted on FR-4 board of 1inch2, 2 oz Cu and 10sec 2. Steady state 3. Measured at source pin when the device is mounted on FR-4 board in steady state
3/13
Electrical characteristics
STK20N3LLH5
2
Electrical characteristics
(TCASE=25C unless otherwise specified) Table 4.
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on)
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 250 A, VGS= 0 VDS = Max rating, VDS = Max rating,Tc=125C VGS = 22 V VDS= VGS, ID = 250 A VGS= 10 V, ID= 10 A VGS= 4.5 V, ID= 10 A 1 0.006 0.008 Min. 30 1 10
100
Typ.
Max.
Unit V A A nA V
2.5 0.007 0.01
Table 5.
Symbol Ciss Coss Crss Qg Qgs Qgd Qgs1 Qgs2
Dynamic
Parameter Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge Pre Vth gate-to-source charge Post Vth gate-to-source charge Gate input resistance Test conditions Min. Typ. 1370 260 33 8.5 TBD TBD TBD TBD Max. Unit pF pF pF nC nC nC nC nC
VDS =25 V, f=1 MHz, VGS=0
VDD=24 V, ID = 20 A VGS =4.5 V (see Figure 3) VDD=24 V, ID = 20 A VGS =4.5 V (see Figure 8) f=1 MHz Gate DC Bias = 0 Test signal level = 20 mV open drain
RG
TBD
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STK20N3LLH5
Electrical characteristics
Table 6.
Symbol td(on) tr td(off) tf
Switching times
Parameter Turn-on delay time Rise time Test conditions VDD= 24 V, ID= 10 A, RG=4.7 , VGS=4.5 V (see Figure 2) VDD= 24 V, ID= 10 A, RG=4.7 , VGS=4.5 V (see Figure 2) Min. Typ. TBD TBD Max. Unit ns ns
Turn-off delay time Fall time
TBD TBD
ns ns
Table 7.
Symbol ISD ISDM(1) VSD(2) trr Qrr IRRM
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward on Voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD= 24 A, VGS=0 ISD= 24 A, di/dt = 100 A/s, VDD=20 V, Tj=150C (see Figure 7) TBD TBD TBD Test conditions Min. Typ. Max. 20 80 1.1 Unit A A V ns nC A
1. Pulse width limited by package 2. Pulsed: pulse duration = 300s, duty cycle 1.5%
5/13
Test circuits
STK20N3LLH5
3
Figure 2.
Test circuits
Switching times test circuit for resistive load Figure 3. Gate charge test circuit
Figure 4.
Test circuit for inductive load Figure 5. switching and diode recovery times
Unclamped inductive load test circuit
Figure 6.
Unclamped inductive waveform
Figure 7.
Switching time waveform
6/13
STK20N3LLH5 Figure 8. Gate charge waveform
Test circuits
Id Vds Vgs
Vgs(th)
Qgs1 Qgs2
Qgd
7/13
Package mechanical data
STK20N3LLH5
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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STK20N3LLH5
Package mechanical data
Table 8.
Ref.
PolarPAK(R) (option "S") mechanical data
mm Min. Typ. 0.80 Max. 0.85 0.05 0.48 0.41 2.19 0.89 0.23 0.20 6 5.74 5.01 4.75 0.23 0.45 0.31 0.45 1.92 0.38 4.22 0.24 4.30 3.43 0.22 0.05 0.15 3.48 0.56 1.20 3.90 0.18 0 10 0.36 12 0 0.20 3.64 0.76 0.25 4.10 0.95 4.50 3.58 4.70 3.73 1.97 0.43 4.37 0.41 0.56 0.51 0.56 2.02 0.48 4.52 0.58 0.51 2.29 1.04 0.33 0.25 6.15 5.89 5.16 4.90 0.68 0.61 2.39 1.19 0.43 0.30 6.30 6.04 5.31 5.05 0.019 0.016 0.086 0.035 0.009 0.008 0.236 0.226 0.197 0.187 0.009 0.018 0.012 0.018 0.075 0.014 0.166 0.009 0.169 0.135 0.009 0.002 0.006 0.137 0.022 0.047 0.154 0.007 10 0.014 12 0.008 0.143 0.030 0.010 0.161 0.037 0.177 0.141 0.185 0.147 0.077 0.016 0.172 0.016 0.022 0.020 0.022 0.079 0.018 0.178 0.023 0.020 0.090 0.041 0.013 0.010 0.242 0.232 0.203 0.193 Min. 0.030 inch Typ. 0.031 Max. 0.033 0.002 0.027 0.024 0.094 0.047 0.017 0.012 0.248 0.238 0.209 0.199
A A1 b1 b2 b3 b4 b5 c D D1 E E1 H1 H2 H3 H4 I1 J1 K1 K4 M1 M2 M3 M4 P1 T1 T2 T3 T4 T5 <
0.75
9/13
Package mechanical data
STK20N3LLH5
Figure 9.
PolarPAK(R) (option "S") drawings
10/13
STK20N3LLH5 Figure 10. Recommended PAD layout
Package mechanical data
11/13
Revision history
STK20N3LLH5
5
Revision history
Table 9.
Date 03-Sep-2008
Document revision history
Revision 1 First release Changes
12/13
STK20N3LLH5
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